Business Wire

Mentor Graphics HDL Designer Saves Months of Design Effort with Concurrent HDL Checking

WILSONVILLE, Ore.--(BUSINESS WIRE)--Oct. 7, 2005--Mentor Graphics Corporation (Nasdaq:MENT), the leader in standards-based digital IC design creation, analysis, synthesis, and management tools, today ...
EDN

Mentor provides concurrent HDL checking for FPGA and ASIC designers

Mentor Graphics released a new concurrent design checking and creation environment for FPGA and ASIC design teams working with Verilog, SystemVerilog, and VHDL design languages. The capability is ...
Semiconductor Engineering

The Growing Need For Concurrent Design

The move toward concurrent design is escalating at advanced nodes, driven more by the need to ensure that everything works than previous efforts aimed at efficiency and time-to-market. While the ...