Semiconductor Engineering

Power-Aware Test: Addressing Power Challenges In DFT And Test

Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design ...
Semiconductor Engineering

A Practical Approach To DFT For Large SoCs And AI Architectures, Part II

Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that ...
Electronic Design

DFT Propels SoC IC Testing

The Design-for-Test (DFT) methodology is a strong driving force in the cost-effective testing of large-volume commodity items with very short life cycles, like system-on-chip (SoC) devices. It will ...
EDN

Is DFT ready for prime time?

Over the last few years, design-for-test (DFT) chip-testing techniques such as internal scan (ISCAN), automatic test-pattern generation (ATPG), built-in self-test (BIST), and boundary scan (BSCAN) ...
EDN

Managing Emerging Test Complexity

For device manufacturers, emerging semiconductor capabilities offer a dramatic increase in device complexity and density allowing the development of highly integrated system-on-a-chip (SOC) products, ...