Electronic Design

Full-Chip High-Level Synthesis Tool Adds SystemC Support

High-level synthesis (HLS) continues to grow in favor among beleaguered system-on-a-chip (SoC) design teams. At the same time, EDA vendors continue to increase the capabilities of their tools. The ...
Semiconductor Engineering

Formal Verification Of Synthesizable C++/SystemC Designs

High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this ...
Business Insider

Mentor Ushers in New Era of C++ Verification Signoff with New Catapult Tools and Solutions

New Catapult DesignChecks tool finds bugs early in C++/SystemC HLS code requiring no testbench – saving designers days or weeks of debugging. New Catapult Coverage provides synthesis-aware RTL-like ...
EDN

DESIGN TOOLS: Synthesis tool adds support for SystemC

Santa Cruz, Calif. — When Mentor Graphics Corp. introduced its Catapult C synthesis tool last year, the company eschewed SystemC in favor of ANSI C++. This week, however, Mentor will announce that ...
Semiconductor Engineering

High-Level Synthesis: It’s Still Hardware Design

Hardware design using HLS is no different than the typical ASIC/FPGA design flow with the exception that C++/SystemC is being used along with HLS to create the RTL instead of hand coding it. The ...