Forbes

IBM Goes Vertical To Scale Transistors

At the December 2021 IEDM conference (a conference for people who design advanced semiconductors), IBM announced it was turning transistors on their heads to keep Moore’s Law scaling alive. The new ...
Electronic Design

Physical Verification in the Age of One Billion Transistors, One Thousand Design Rules, and Million Dollar Mask Sets

Physical-verification cycle time increases significantly with each new process generation. Rule-deck complexity contributes considerably to this effect. The number of design rules grows rapidly as ...
EDN

Freemium analog layout tool facilitates quick, easy, and accurate physical information

Animate Preview, the analog layout design tool that generates physical information after a schematic is loaded, is now available for complimentary download and installation. It provides engineers with ...
EDN

Low power implementation techniques for ASIC physical design

In the semiconductor domain, the operating frequency of devices and the number of transistors in a single module increase over time. In this article, we will look at widely known low power ...